The present invention relates generally to semiconductor fabrication, and more particularly relates to techniques for reducing a number of steps and/or lithographic masks employed while fabricating complementary self-aligned transistors.
The fabrication of integrated circuit (IC) devices, as used in very large scale integration (VLSI) applications, typically involves a complex sequence of well-known lithographic processing steps. Several of these processing steps are described, for example, in the text by Alan B. Grebene entitled xe2x80x9cBipolar and MOS Analog Integrated Circuit Design,xe2x80x9d John Wiley and Sons, 1984, Chap. 1, pp. 1-51, which is incorporated herein by reference. Accordingly, a detailed discussion of such conventional IC processing steps will not be presented herein.
Self-aligned bipolar transistors are known in the prior art. These transistors are advantageous in that they inherently have significantly reduced parasitics (e.g., capacitance), thus enabling the transistors to achieve faster speeds. Two common types of self-aligned bipolar transistors conventionally used in the industry are those having spacers outside the emitter of the device and those having spacers inside the emitter. Transistors having spacers outside the emitter generally employ one polysilicon layer for the emitter formation and are thus referred to as single-poly self-aligned transistors. Transistors having spacers inside the emitter generally use two polysilicon layers and are often referred to as double-poly self-aligned transistors.
Conventional approaches to manufacturing self-aligned complementary transistors involve the use of several additional masks or reticles and corresponding fabrication steps. For example, using an npn bipolar or bipolar complementary metal-oxide-semiconductor (BiCMOS) technology, the inclusion of a high performance vertical pnp transistor generally requires seven additional masks. Any increase in the number of masks and/or processing steps undesirably translates to an increase in the overall cost of IC fabrication. Moreover, each additional fabrication step presents an opportunity for the introduction of impurities into the resulting device, thus negatively impacting the manufacturing yield.
Accordingly, it is desirable to reduce the number of masking steps used for fabricating self-aligned complementary bipolar transistors to improve manufacturing yield and reduce the manufacturing cost.
The present invention provides techniques for reducing a number of fabrication steps and/or lithographic masks employed in the manufacture of self-aligned complementary bipolar transistors without increasing a complexity of the fabrication process. A reduction in the number of fabrication steps and/or masks reduces an overall cost and time of the fabrication process. Additionally, by reducing the number of fabrication steps, the present invention reduces a likelihood of introducing impurities into the IC device, thus improving the manufacturing yield.
In accordance with one aspect of the invention, a method of fabricating complementary bipolar transistors on at least a portion of a semiconductor wafer includes the steps of forming a first electrode corresponding to a first transistor, and a second electrode corresponding to a second transistor which is complementary to the first transistor. The first and second electrodes are formed on an upper surface of the semiconductor wafer. A first impurity is selectively introduced into the first and second electrodes. A third electrode is then formed corresponding to the first transistor, the third electrode being self-aligned with and electrically isolated from the first electrode. Likewise, a fourth electrode is formed corresponding to the second transistor, the fourth electrode being self-aligned with and electrically isolated from the second electrode. A second impurity is selectively introduced into the third and fourth electrodes. In addition, a first active region of the first transistor and a first active region of the second transistor are formed, whereby at least a portion of the first impurity associated with the first and second electrodes diffuses into the first active regions of the first and second transistors. Similarly, a second active region of the first transistor and a second active region of the second transistor are formed, whereby at least a portion of the second impurity associated with the third and fourth electrodes diffuses into the second active regions of the first and second transistors.
In an illustrative embodiment of the present invention, two layers of polysilicon are utilized which may either doped by implantation or doped in-situ, for example during a deposition step. An npn transistor is formed such that an npn emitter polysilicon and dopant (n-type) are also used to form a pnp base electrode. Similarly, a pnp transistor is formed such that a pnp emitter polysilicon and dopant (p-type) are also used to form an npn base electrode. In the npn transistor, the base electrode is self-aligned to and electrically isolated from the emitter electrode. In the pnp transistor, the emitter electrode is self-aligned to and electrically isolated from the base electrode.
These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.